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LaMeres CPU verilog code for Spartan 7 FPGA

`timescale 1ns / 1ps // Code was provided by Brock J. LaMeres // See his book “Introduction to Logic Curcuits & Logic Design with Verilog” (2nd edition) // for more detailed discussions // // It was modified for Spartan7 and pared down for simplicity // Only 3 instructions LDA, STA, and BRA to demonstrate simple […]


module Mux2_1(out,cntrl,in1,in2); input cntrl,in1,in2; output out; assign out = cntrl ? in1 : in2; endmodule


module mux2tb; wire out; reg cntrl,in1,in2; Mux2_1 uut(out,cntrl,in1,in2); initial begin $monitor($time,” out=%b,cntrl=%b,in1=%b,in2=%b”,out,cntrl,in1,in2); cntrl=0;in1=0;in2=0; #1 in1=1;in2=0; #1 in1=0;in2=1; #1 in1=1; in2=1; #1 cntrl=1; #1 in1=0;in2=0; #1 in1=1;in2=0; #1 in1=0;in2=1; #1 in1=1; in2=1; #10 $finish; end endmodule


module usart_top #(parameter BPS_CNT = 16’d108) //波特率参数 = 100M/92160 ( input sys_clk, sys_rst, //使能高电平有效,低电平复位 input uart_rxd, output uart_txd, output reg [7:0] FRE_code, //8位 中心频率码 output reg [7:0] ATT_code1,ATT_code2, ATT_code3, ATT_code4, //8位 衰减码 output reg [7:0] PHA_code1,PHA_code2,PHA_code3, //8位 相移码 output reg LE //校验成功信号 ); localparam state0 = 4’d0; localparam state1 = 4’d1; localparam state2 = 4’d2; […]

先拼好再 选择性输出

//根据频率来选择表 always @ (posedge sys_clk or negedge sys_rst) begin if(!sys_rst) begin end else begin if(trig_reg[1:0] == 2’b01) begin if(24’d0