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constrained_fifo_vhdlwhiz

library ieee; use ieee.std_logic_1164.all; entity sync_fifo is generic ( FIFO_WIDTH : natural; FIFO_DEPTH : natural ); port ( clk : in std_logic; rst : in std_logic; — Write port wr_en : in std_logic; wr_data : in std_logic_vector(FIFO_WIDTH – 1 downto 0); — Read port rd_en : in std_logic; rd_valid : out std_logic; rd_data : out […]

constrained_fifo_vhdlwhiz

library ieee; use ieee.std_logic_1164.all; entity sync_fifo is generic ( FIFO_WIDTH : natural; FIFO_DEPTH : natural ); port ( clk : in std_logic; rst : in std_logic; — Write port wr_en : in std_logic; wr_data : in std_logic_vector(FIFO_WIDTH – 1 downto 0); — Read port rd_en : in std_logic; rd_valid : out std_logic; rd_data : out […]

variable_clock.vhd

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity variable_clock is Port ( clk_i : in STD_LOGIC; resetn_i : in STD_LOGIC; ticks_i : in STD_LOGIC_VECTOR (7 downto 0); clk_o : out STD_LOGIC ); end variable_clock; architecture Behavioral of variable_clock is signal s_counter: natural range 0 to 2**ticks_i’length-1 := 0; signal s_clk_out: STD_LOGIC := ‘0’; begin process (clk_i, […]

Sumador.vhd

–https://vasanza.blogspot.com –Library library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; –Entity entity Sumador is generic ( n: integer :=8);–

Maximum to minimum ordering of values in #RAM memory using #VHDL

–https://vasanza.blogspot.com — MSS library ieee; use ieee.std_logic_1164.all; entity MSS is port (clk, resetn, start,WriteData, Fin_j, AmenB, Fin_i: in std_logic; enj,ldj,WritingData,s1,eni,ldi,enReg,Sel,enReg2,sel3,sel2,done: out std_logic); end MSS; architecture solv of MSS is type estado is (A,B,C,D,E,F,G,H,I,J,K); signal y: estado; signal entradas: std_logic_vector(4 downto 0); signal salidas: std_logic_vector(11 downto 0); begin entradas